Algorithmic Reduction and Optimization of Logic Circuit in area and Power Tradeoffs’ with the Help of BDD

The design complexity and increasing speed of very-large-scale integration (VLSI) chips implies a significant increase in the power consumption. So, many different design approaches have been developed by researchers to reduce the power. This paper presents an algorithmic technique based on hybridizing Symbolic Manipulation Techniques based on BDDs with more traditional explicit solving algorithms. To validate the approach, the graph colouring problem has been selected as a hard-to-solve problem, and an optimized solution based on hybrid techniques has been implemented. Experimental results on a set of benchmarks derived from the CAD for VLSI area show the applicability of the approach to graphs with millions of vertices in a limited CPU time. Boolean functions can be graphically manipulated to reduce the number of nodes, hence the area, when implemented as Binary decision diagrams. So here, ordering of BDD nodes plays a very important role. Most of the algorithms for variable ordering of OBDD have focus on area minimization. Hence, for minimizing the power consumption, suitable input variable ordering is required. So, to find an optimal variable, three algorithms have been used namely genetic algorithm based technique, a branch and bound algorithm and a scatter search algorithm in this paper. Experimental results show a substantial reduction in area and power. Also, the switching activity of the circuit is calculated. Moreover, a comparison is made between all the above techniques.